Test Chips

Thermal and Bumped Test Chips for Testing Services

Since 1995, many industry and academic customers have used the portfolio of thermal and flip chip test chips that has been developed by Kokomo Semiconductors’ engineers and technicians. Initially created to characterize and develop our internal assembly and packaging technologies, these test chips have also proven useful to a number of other researchers in developing their products and processes. All are commercially available.

Kokomo Semiconductors’ test chips are manufactured on 125mm (5 inch) wafers. The test chips can be delivered in various forms, such as an unbumped wafer, bumped wafer, tape and reel, or waffle pack. Various solders are available for the bumped wafers. The PB and FA series can also be sawn to various dimensions. Polyimide overcoat, backside metal and wafer thinning are also available options on some test chips.

For pricing and ordering information, please contact us.

PB Series

Kokomo Semiconductors’ PB (Perimeter Bump or Bond) series of test chips are designed to simulate I/O of CMOS-like devices at various pad pitches. These test vehicles form the basis of a useful die standard for the testing services and evaluation of flip chip applications as a function of various bump materials or assembly variables. A limited subset of PB series die has been designated for wire bond applications. The standard chip size is 200 mil X 200 mil (5040 microns X 5040 microns).

FBT250 and FBT500

The FBT250 and FBT500 are the original PB series. Kokomo Semiconductors’ FBT250 test chip is designed with I/O pads on 18 mil (457.2 micron) pitch located on the peripheral of the chip. The 250 mil X 250 mil (6350 micron X 6350 micron) FBT250 chip contains 48 pads giving 24 daisy chain pairs. Kokomo Semiconductors’ FBT500 test chip is designed with I/O pads on 18 mil (457.2 micron) pitch located on the peripheral of the chip. The 500 mil X 500 mil (12700 micron X 12700 micron) FBT500 chip contains 96 pads giving 48 daisy chain pairs.

FA Series

Kokomo Semiconductors’ FA (Full Array) series of test chips are designed to simulate the I/O of CMOS-like devices at various pad pitches. These test vehicles form the basis of a useful die standard for the evaluation of flip chip applications as a function of various bump, materials, or assembly variables. The FA series takes the PB series and fills each row with additional daisy chained pairs. A limited subset of FA series chips has been designated for wire bond applications. The standard chip size is 200 mil X 200 mil (5040 microns X 5040 microns).

PST Series

Kokomo Semiconductors’ PST series of Thermal Test Chips are used to determine thermal characteristics of a package, such as thermal resistance Junction to Case or Junction to Ambient. These Thermal Test Chips incorporate a heating element and typically two independent methods for on-die temperature monitoring during testing services as well as other times.

One on-die temperature monitor utilizes a serial five diode temperature sense network. A four pad layout allows Kelvin connections. The second temperature monitoring circuit uses a bridge network. PST4 or larger chips also repeat the serial five diode temperature sense network in all four corners of the chip.

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